Computer Organization and Design: The Hardware Software Interface: ARM Edition (The Morgan Kaufmann Series in Computer Architecture and Design)
The new ARM Edition of Computer Organization and Design features a subset of the ARMv8-A architecture, which is used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies, and I/O.
With the post-PC era now upon us, Computer Organization and Design moves forward to explore this generational change with examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Updated content featuring tablet computers, Cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures is included.
An online companion Web site provides links to a free version of the DS-5 Community Edition (a free professional quality tool chain developed by ARM), as well as additional advanced content for further study, appendices, glossary, references, and recommended reading.
indicates speed, cost, and size: the closer to the top, the faster and more expensive per bit the memory; the wider the base of the layer, the bigger the memory. Dependability via Redundancy Computers not only need to be fast; they need to be dependable. Since any physical device can fail, we make systems dependable by including redundant components that can take over when a failure occurs and to help detect failures. We use the tractor-trailer as our icon, since the dual tires on each
graphics subsystems declined in price from $50,000 to $200. ■ Performance increased from 50 million pixels per second to 1 billion pixels per second and from 100,000 vertices per second to 10 million vertices per second. ■ Native hardware capabilities evolved from wireframe (polygon outlines) to flat shaded (constant color) filled polygons, to smooth shaded (interpolated color) filled polygons, to full-scene anti-aliasing with texture mapping and rudimentary multitexturing. Fixed-Function
Next-state outputs, D-10, D-12–13 example, D-12–13 implementation, D-12 logic equations, D-12–13 truth tables, D-15 No Redundancy (RAID 0), OL5.11-4 No write allocation, 394 Nonblocking assignment, B-24 Nonblocking caches, 344, 472 Nonuniform memory access (NUMA), 518 Nonvolatile memory, 22 Nops, 314 nor (NOR), 64 NOR gates, B-8 cross-coupled, B-50 D latch implemented with, B-52 NOR operation, 89, A-54, E-25 NOT operation, 89, A-55, B-6 Numbers binary, 73 computer versus
Historical Perspective and Further Reading 3.12 Exercises 4. The Processor 4.1 Introduction 4.2 Logic Design Conventions 4.3 Building a Datapath 4.4 A Simple Implementation Scheme 4.5 An Overview of Pipelining 4.6 Pipelined Datapath and Control 4.7 Data Hazards: Forwarding versus Stalling 4.8 Control Hazards 4.9 Exceptions 4.10 Parallelism via Instructions 4.11 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines 4.12 Going Faster: Instruction-Level Parallelism and Matrix
numbers are of the form F involves the value in the fraction field and E involves the value in the exponent field; the exact relationship to these fields will be spelled out soon. (We will shortly see that MIPS does something slightly more sophisticated.) These chosen sizes of exponent and fraction give MIPS computer arithmetic an extraordinary range. Fractions almost as small as 2.0ten×10−38 and numbers almost as large as 2.0ten×1038 can be represented in a computer. Alas, extraordinary